1. Field of the Invention
The present invention relates to an electrically writable and erasable non-volatile semiconductor memory device (flash memory) operable on power from a single power supply.
2. Description of the Related Art
There is an electrically writable and erasable non-volatile semiconductor memory device (hereinafter called "flash memory").
FIG. 1 shows an example of the structure of this flash memory. In FIG. 1 an address signal is supplied via address buffers 1 to row decoders 2.
A voltage switching circuit 11 is supplied with a power supply voltage Vcc, a first high voltage Vpp for data writing and control signals PG and PGVER and outputs a voltage Vpp2. At the time of writing data in memory cells 4, the voltage switching circuit 11 outputs a first high voltage (e.g., 12 V) higher than the power supply voltage Vcc as the voltage Vpp2. At the time of write verifying, the voltage switching circuit 11 outputs a second high voltage lower than the first high voltage Vpp but higher than the supply voltage Vcc as the voltage Vpp2. The write verify is a process to check whether or not the threshold voltage of a data-written memory cell transistor has risen to a sufficient level.
Each row decoder 2 decodes the received address signal, and selects a word line connected to the gates of those memory cells 4 in the selected row to apply the voltage from the voltage switching circuit 11 to the word line. That is, in writing data, each row decoder 2 applies the first high voltage Vpp to the Gate of the selected memory cell 4. The threshold voltage of the memory cell transistor 4 where data has been written rises higher than those of unwritten memory cell transistors 4, and this memory cell transistor 4 becomes non-conductive at the time of normal data reading. When write verify is to be executed, the row decoder 2 applies the second high voltage to the gate of the selected memory cell transistor 4 to read data therefrom, and checks if this memory cell transistor 4 is non-conductive.
FIG. 2 illustrates the arrangement of the essential portions of the voltage switching circuit 11. With the illustrated structure, at the time of normal data reading, a control circuit (not shown) sets PG=0 V, PGVER=0 V and PG+PGVER=Vcc. This renders N type MOS transistors M1 and M2 non-conductive and an N type depletion transistor M3 conductive, so that read voltage (power supply voltage) Vcc is output as an output voltage Vpp2.
At the time of data writing, the control circuit sets PG=Vpp, PGVER=0 V and PG+PGVER=0 V. Consequently, the N type MOS transistor M1 becomes conductive, causing the first high voltage Vpp to be output as the output voltage Vpp2.
At the time of write verify, the control circuit sets PG and PG+PGVER to 0 V, and PGVER to Vpp. As a result, the N type MOS transistor M2 becomes conductive, causing the second high voltage (R2/(R1+R2))Vpp to be output as the output voltage Vpp2. The proper gate voltage of a target memory cell transistor at the write verify time can be set by properly determining the resistances R1 and R2.
If a flash memory is of a type that is externally supplied with only the supply voltage Vcc, the mentioned voltage Vpp should be produced from the supply voltage Vcc within the chip using a booster circuit. Generally, such a booster circuit has a small current drive capacity, which lowers the speed of switching the gate of each memory cell transistor 4 and thus slowing the operation speed of the whole memory device.